The present invention relates to optical chips and, more particularly, to optical chip packaging.
Opto-electronic chips have the ability to provide huge optical bandwidth. However, that data sent or received optically needs to get into and out of the chips electrically. Thus, the amount of electronic I/O needs to be large so as not to unduly create a bottleneck in the flow of data. Given the constraints on how fast an individual electrical line can be, the requirement for a large amount of I/O typically translates into a large number of I/O pads on the chip. However, the ability to place many electrical I/O connections a chip is counterbalanced by the need to place the I/O connections as close together as possible.
Typically, users of optical modules (containing one or more opto-electronic chips) or designers of components on which those modules mount, like to have the modules configured so that the modules will mount onto circuit boards and have the electrical I/O connections at a 90 degree angle to the optical I/O connection. Thus, it is desirable to allow the electrical signals to traverse a 90 degree bend.
Moreover, to the extent optical or opto-electronic chips are connected to flex circuits, they are typically connected using wirebonding techniques. Such techniques introduce undesirable parasitic capacitance, which is particularly detrimental to high frequency operation.
Since a goal with these modules is to bring data in and out as quickly as possible, it is important to ensure that the speed of each of the electrical connections to the chip can support the highest bandwidth (i.e. data rates) possible.
The use of flexible circuits to make 90 degree electrical turns to allow electrical access to occur at a right angle to optical access per se is known, for example, from D. Pommerrenig, D. Enders, T. E. Meinhardt, xe2x80x9cHybrid Silicon Focal Plane Development: an Update,xe2x80x9d SPIE Vol 267, Staring Infrared Focal Plane Technology, (1981) at p. 23. This reference describes an approach for soldering or welding cables to the backside of an optical chip for 90 degree turning. A chip produced using the prior art approach is shown in FIG. 1. Illustrated is a detector 2, a flex chip 4, a module base 6 and a MUX chip 10. However, the approach suffers from the same problems noted above, as is evident in FIG. 1, namely providing optical access inhibits access to the device for cooling.
More recent attempts have followed the same basic approach, but have electrically connected the electronic chip to the flex circuit using wirebond techniques, for example, as done with Agilent Technologies PONI-1 POSA Package, or using other edge connecting metalized connections, for example, beamleads.
All the foregoing approaches however have used a single-side access flex circuit.
In addition, because wirebonds are used in the prior art, the use of wirebonds limits the number of electrical connections possible between the electronic chip and the flex circuit (since the wirebonds require a larger electrical attachment area than a corresponding number of connections using flip-chip connection techniques. Wirebonds or other extended metal connectors coming off a chip also have large capacitances and inductances which limit the speed of the off-chip connection and also increases the electrical crosstalk/noise between adjacent electrical channels.
FIG. 2 shows one such example of a flex circuit arrangement that allows the optical devices to be placed on top of the electronic chip, but the configuration is still limited by off-electronic-chip wiring and still inhibits access to the non-active side for cooling. Illustrated in FIG. 2 is an optional auxiliary chip 12, a chip to flex connection 14 an electronic chip 16 and an optical device 20.
Presently, there is no way to package an optical chip or an optical chip with an electronic chip (i.e. create an opto-electronic chip) that allows for close connections between the two, reduces parasitic capacitance and inductance, provides unobstructed optical access while allowing for connection of a heatsink to the chip for cooling.
Our invention involves an approach to the integration of optical or opto-electronic chips with electrical connectors.
Our approach circumvents the need for off-chip electronic wiring or electrical lead-oriented connection approaches. Note that the flex prior art of circuit FIG. 2 exists to the right-side of the electronic chip. Hence it is difficult, if not impossible, to effectively attach a heatsink to aid in cooling the electronic chip, since it can not be placed on the front of the chip without impeding optical access and it cannot be attached to the back of the electronic chip (on the rightside of the chip of FIG. 2 because the flex circuit is in the way.
One advantage obtainable in accordance with the invention is the approach allows high density, high speed, electrical connections to be made to dense opto-electronic chips while allowing optical access to those chips.
Another achievable advantage is the ability to provide the above high speed connections while still allowing for easy optical access for edge-mounted optical components.
Advantageously, since the optical component community is moving toward (or already uses) flex circuits to connect optical modules to circuit cards, our technique does not xe2x80x9cbuck the trendxe2x80x9d but rather goes along with so as to allow for greater acceptance.
In addition, this technique provides the ability to integrate electronic I/O pads on optoelectronic chips in multi-tiered rows. Still further, this technique allows the multi tiered rows to even be away from the optical or opto-electronic chip edge.
Still further, our technique minimizes parasitic electronic capacitance and inductance on flex circuit-to-chip connections.
In addition, the technique of placing the optical or opto-electronic chip on the backside of the flex allows for easy heat sink access to the chip without impeding or interfering with the optical path, irrespective of whether the chip contains topside active or backside (also called bottom) active (also called bottom active) devices.
The advantages and features described herein are a few of the many advantages and features available from representative embodiments and are presented only to assist in understanding the invention. It should be understood that they are not to be considered limitations on the invention as defined by the claims, or limitations on equivalents to the claims. For instance, some of these advantages are mutually contradictory, in that they cannot be simultaneously present in a single embodiment. Similarly, some advantages are applicable to one aspect of the invention, and inapplicable to others. Thus, this summary of features and advantages should not be considered dispositive in determining equivalence. Additional features and advantages of the invention will become apparent in the following description, from the drawings, and from the claims.